This invention relates to a semiconductor device and, in particular, a semiconductor device containing a DMOS FET or a conductive modulation type MOS FET.
DMOS FET (double diffusion insulating gate longitudinal FET) or a conductive modulation type MOS FET has a high-speed switching characteristic and has been used primarily as a high-power type semiconductor device due to its small input loss and high input impedance. For example, DMOS FET contains an n-type drain region, a plurality of p-type base regions formed in the drain region, source regions formed in the base region, a source electrode formed on the source region and a gate electrode formed over the drain region between two adjacent base regions through an insulating layer. In the conductive modulation type MOS FET, a p-type anode region is formed under the aforementioned n-type drain region.
For ease in understanding this invention a semiconductor device containing a conventional conductive modulation type MOS FET will be explained below with reference to FIG. 1. FIG. 1 shows a plan view showing semiconductor device 10 having metal (aluminum) gate electrode wiring 2, aluminum source electrode 1 and gate electrode 3. The metal gate electrode wiring 2 electrically contacts gate electrode 3, formed of polysilicon. Aluminum source electrode 1 is patterned by aluminum gate electrode wiring 2 to provide a predetermined pattern, but is not divided into a plurality of aluminum source electrode branch sections. Gate electrodes 3, formed of polysilicon, are located under aluminum source electrode 1.
In semiconductor device 10, including metal gate electrode wiring 2 shown in FIG. 1, if the dimension of the semiconductor chip or a drain region formation region is increased to about 8.0.times.8.0 mm, gate electrode 3 of polysilicon becomes extremely longer and, as a result, its resistance becomes too great to be disregarded and, at the same time, its input capacity becomes greater. This causes a reduction in switching speed, an increase in input loss and a transient degeneration in drain current distribution. That is, when a MOS FET which is now in an on state is rendered off, the drain current distribution in the chip becomes nonuniform. In other words, the drain current is concentrated into that portion of the semiconductor device where the OFF-time delayed MOS FET is located, thus resulting in a breakdown of the aforementioned device portion. This causes a decrease in latching-up current, in the case of the conductive modulation type MOS FET, and a lowering in the V.sub.DSX(SUS) capability (i.e., a surge voltage absorption capability when the MOS FET is switched OFF) in the case of DMOS FET, with the result that the breakdown load current of the MOS FET at the switching-off time is lowered under such an inductive load as when a motor is driven.